1. Field of the Invention
The present invention relates generally to motor drive apparatus for controllably driving electric motors, and more particularly to an improved motor drive apparatus which includes a motor drive circuit with a bridge composed of four field effect transistors (hereinafter also referred to as "FETs") and is capable of reliably detecting presence or absence of an ON-state trouble in each of the FETs in the motor drive circuit.
2. Description of the Related Art
Among various types of the conventionally-known motor drive apparatus is the one which includes a motor drive circuit with a bridge composed of four FETs as typically illustrated in FIG. 5.
The illustrated bridge-type motor drive circuit 50 of FIG. 5 includes a total of four n-channel FETs Q1 to Q4. The first and second FETs Q1 and Q2 have their drains connected to the higher-potential or plus electrode of a battery Eo having a 12V capacity, for example, and the third and fourth FETs Q3 and Q4 have their sources connected to the lower-potential or minus (or ground commonly abbreviated "GND") electrode of the battery Eo. The source of the first FET Q1 and the drain of the third FET Q3 are connected with each other via a terminal M1, and similarly the source of the second FET Q2 and the drain of the fourth FET Q4 are connected with each other via a terminal M2. Electric motor 51 is connected between the terminals M1 and M2.
By activating or turning on the gate G1 of the first FET Q1 with a pulse-width-modulated (PWM) control signal and simultaneously turning-on the gate G4 of the fourth FET Q4, an electric current is caused to flow from the battery Eo, through the first FET Q1, terminal M1, motor 51, terminal M2 and fourth FET Q4, to the ground, so that the motor 51 is rotated in a forward direction; note that in order to thus rotate the motor in the forward rotation, it is also necessary for the gates G2 and G3 of the second and third FETs Q2 and Q3 to remain turned off.
Then, by activating or turning on the gate G2 of the second FET Q2 with a similar pulse-width-modulated (PWM) control signal and simultaneously turning on the gate G3 of the third FET Q3, an electric current is caused to flow from the battery Eo, through the second FET Q2, terminal M2, motor 51, terminal M1 and third FET Q3, to the ground, so that the motor 51 is rotated in a reverse direction; note that in order to thus rotate the motor the reverse rotation, it is also necessary for the gates G1 and G4 of the first and fourth FETs Q1 and Q4 to remain turned off.
Namely, with the motor drive circuit 50, the motor 51 is rotated in the forward or reverse direction by turning on the gate G1 of the first FET Q1 or the gate G2 of the second FET Q2 with the PWM control signal while, at the same time, turning on the gate G4 of the fourth FET Q4 or the gate G3 of the third FET Q3.
In the aforesaid conventional motor drive apparatus, a close check is made to see whether or not the four FETs Q1 to Q4 constituting the bridge circuit have an ON-state trouble, i.e., a short circuit.
More specifically, in the illustrated motor drive circuit 50 of FIG. 5, the "ON-state trouble check" on the four FETs Q1 to Q4 is made by detecting voltages of the motor 51 at the terminals M1 and M2 with the respective gates G1-G4 of all the FETs Q1 to Q4 turned off. Namely, in a situation where all the FETs Q1 to Q4 are in a normal operating condition (i.e., free of ON-state trouble or short circuit, a substantial zero voltage is detected at each of the terminals M1 and M2. However, even when the third or fourth FET Q3 or Q4 has the ON-state trouble, the zero voltage would be detected at each of the terminals M1 and M2 just as in the case where all the FETs Q1 to Q4 are in the trouble-free normal operating condition; thus, it has been impossible to accurately determine whether the third or fourth FET Q3 or Q4 is in the trouble-free normal operating condition or has the ON-state trouble.
Further, when the gate G1 of the first FET Q1 is turned on in the motor drive circuit 50 from a situation where all the gates G1-G4 of the first to fourth FETs Q1 to Q4 have been placed in the OFF state, a 12V voltage would be detected at each of the terminals M1 and M2. In this case, if the ON-state trouble occurs in the third or fourth FET Q3 or Q4 and an ON-state resistance of one of the malfunctioning third and fourth FETs Q3 and Q4 (i.e., resistance between the drain and source (drain-source resistance) of the third or fourth FET Q3 or Q4) is in the order of 1K.OMEGA. (the ON-state resistance in the normal operating condition is only tens of m.OMEGA.), then the 12V potential would appear at each of the terminals M1 and M2, making it impossible to appropriately distinguish between the case where the third or fourth FET Q3 or Q4 has the ON-state trouble and the case where the all the FETs Q1 to Q4 are in the trouble-free normal operating condition.